EVAL1201/AA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EVAL1201/AA' PDF : 20 Pages View PDF
TSA1201
Clock input
The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.
Power consumption optimization
The internal architecture of the TSA1201 enables
to optimize the power consumption according to
the sampling frequency of. For this purpose, a
resistor is placed between IPOL and the analog
Ground pins. Therefore, the total dissipation is
adjustable from 0.5Msps up to 50Msps. This
feature is of highest importance when power
saving conditions the application.
The TSA1201 will combine highest performances
and lowest consumption at 50Msps when Rpol is
equal to 12kΩ.
At lower sampling frequency range, this value of
resistor may be adjusted in order to decrease the
analog current without any degradation of
dynamic performances.
As an example, 40mW total power consumption is
achieved at 5 Msps with Rpol equal to 190kΩ and
35mW is dissipated at 1Msps with Rpol equal to
350kΩ.
The table below sums up the relevant data.
Figure 7 describes the behaviour of the converter
as sampling frequency increases and shows the
optimum in terms of analog current and
polarization resistor.
Total power consumption optimization
depending on Rpol value
Fs (Msps)
5
35
50
Rpol (kΩ)
190
29
12
Optimized
40
power (mW)
100
150
Figure 7 : Optimized power consumption
Fin=1MHz
200
180
160
140
120
100
80
60
40
20
0
5
ICCA
RPOL
25
45
65
Fs(MHz)
70
60
50
40
30
20
10
0
85
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is mandatory for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is essential to prevent noise from
coupling onto the input signal.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.
- Choose component sizes as small as possible
(SMD).
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