EVAL1203/BA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EVAL1203/BA' PDF : 30 Pages View PDF
TSA1203
The applications requiring single-ended inputs
can be configured like reported on Figure 7 for an
AC-coupled input or on Figure 8 for a DC-coupled
input.
In the case of AC-coupled analog input, the
analog inputs VIN and VINB are biased to the
same voltage that is the common mode voltage of
the circuit (INCM). The INCM and reference
voltages may remain at their internal level but can
also be fixed externally.
Figure 7 : AC-coupled Single-ended input
Signal source
10nF
50Ω
33pF
100kΩ
100kΩ
VIN
INCM TSA1203
VINB
In the case of DC-coupled analog input with 1V
DC signal, the DC component of the analog input
set the common mode voltage. As an example
figure 8, VREFP and INCM are set to the 1V DC
analog input while VREFM is connected to
ground; we achieve a 2Vpp differential amplitude.
Figure 8 : DC-coupled 2Vpp analog input
Analog
DC
AC+DC
VREFP
VIN
TSA1203
VINB
VREFM
INCM
VREFP-VREFM = 1 V
330pF 10nF 4.7uF
Dynamic characteristics, while not being as
remarkable as for differential configuration, are
still of very good quality.
Clock input
The TSA1203 performance is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to keep the circuit clocked, to
avoid random states, before applying the supply
voltages.
Power consumption
So as to optimize both performance and power
consumption of the TSA1203 according the
sampling frequency, a resistor is placed between
IPOL and the analog Ground pins. Therefore, the
total dissipation is adjustable from 35Msps up to
50Msps.
The TSA1203 will combine highest performances
and lowest consumption at 40Msps when Rpol is
equal to 54kΩ. This value is nevertheless depen-
dant on application and environment.
At lower sampling frequency range, this value of
resistor may be adjusted in order to decrease the
analog current without any degradation of
dynamic performances.
The table below sums up the relevant data.
Figure 9 : Total power consumption optimization
depending on Rpol value
Fs (Msps)
35
40
50
Rpol (kΩ)
28
18
17
Optimized
180
230
255
power (mW)
APPLICATION
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is advised for high speed circuit applications
to provide low inductance and low resistance
common return.
The separation of the analog signal from the
digital part is mandatory to prevent noise from
coupling onto the input signal. The best
compromise is to connect from one part AGND,
DGND, GNDBI in a common point whereas
GNDBE must be isolated. Similarly, The power
supplies AVCC, DVCC and VCCBI must be
separated from the VCCBE one.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
15/21
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