EVAL1401/AB View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EVAL1401/AB' PDF : 19 Pages View PDF
TSA1401
APPLICATION INFORMATION
sampling capacitor will draw/inject a small current
transient on the input signal.
One method to mask this transient current is a
low-pass RC filter as shown on Figures 16 and
Figure 17. A larger capacitor value compared to
the sampling capacitor (appoximately 2pF)
mounted in parallel of the two analog inputs
signals will absorb the transient glitches.
Fig. 15: ADC input equivalent circuit
AVcc
Zin=1/(2ΠCs.Fs)=3.3kΩ (Fs=20MHz)
VIN
Cin=4pF
INCM
AGND
Single-ended signal with transformer:
Using an RF transformer is a good means to
achieve high performance.
Figures 16 describes the schematics. The input
signal is fed to the primary of the transformer,
while the secondary drives both ADC inputs.
Fig. 16: Differential input configuration with
transformer
Analog source
ADT1-1
1:1
50Ω
100pF
VIN
TSA1401
VINB
INCM
330pF 10nF 4.7µF
The internal common mode voltage of the ADC
(INCM) is connected to the center-tap of the
secondary of the transformer in order to bias the
input signal around this common voltage,
internally set to 0.46V. The INCM is decoupled to
maintain a low noise level on this node.
AC coupled differential input:
Figure 17 represents the biasing of a differential
input signal in AC-coupled differential input
configuration. Both inputs VIN and VINB are
centered around the common mode voltage CM,
that can be forced through INCM or supplied
externally (in this case the internal common mode
of the TSA1401 may be left internal at 0.45V,
different from the input common mode value).
Fig. 17: AC-coupled differential input
50Ω
common
mode
10nF
33pF
50Ω 10nF
100kΩ
100kΩ
VIN
INCM TSA1401
VINB
5.2 - Clock management
The converter performances are very dependant
on clock input accuracy, in terms of aperture delay
and jitter. The voltage error induced by the jitter of
the clock is:
Verror=SR.Tj,
where Tj is the jitter of the clock (system clock and
ADC) and,
SR is the slew rate of the input signal:
SR max=2Π.Fin.FS (FS full scale, Fin input signal
frequency)
Verror should be less than an LSB to guarantee no
missing codes. At the end we have:
Verror=2Π.Fin.FS.Tj and Verror< FS/2n
Tj <FS/(2Π.Fs.Fin.2n).
For TSA1401 at 10MHz input frequency, we have
Tj <1ps. Consequently to target the maximum
performances of the TSA1401, the clock applied
should have a jitter below 1ps.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is strongly advised not to switch off the clock
when the circuit is active (power supply on).
14/19
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