EVM629AXF View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'EVM629AXF' PDF : 16 Pages View PDF
Edge629
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
Timing Inputs
Data Interface Digital Inputs
IN/IN* and IN0/IN0* – IN3/IN3* are high speed differen-
tial inputs which require >300 mV of differential input
voltage for reliable switching.
These inputs may receive differential input signals with
amplitudes up to 3.3V. This wide range input voltage com-
pliance allows CMOS signals to drive the Edge629 directly.
The inputs may go all the way up to VCC and still not
cause any saturation. The Edge629 will operate at full
performance under these input conditions.
Do not leave any differential inputs floating as they will be
in an indeterminate state. All unused inputs must be tied
to either a high or low level. Connecting unused timing
inputs to VCC is an acceptable method to make an input
high. However, to make an input low, it must be con-
nected to VEE +2.0V or higher.
Input Mux Select
Each delay channel can select its input from one of two
sources. If Mux Select is high (SEL > SEL*), IN/IN* will
be selected for all four channels. If Mux Select is low
(SEL < SEL*), IN0/IN0* – IN3/IN3* will be selected for
each channel.
All data digital inputs are standard, single ended ECL in-
puts with V = –1.3V relative to VCC. However, all digital
bb
inputs may receive input signals anywhere between VCC
and VEE. This wide input voltage compliance allows CMOS
signals to program the Edge629 without causing satura-
tion problems.
All digital interface inputs are "3.3V rail to rail" CMOS
compatible provided VCC = +3.3V and VEE = –2V.
CK, SDI, and UPDATE all have an internal pull-down resis-
tor network to establish a default condition of a logical 0
when left floating. CS has a large (~50 KΩ) internal pull-
up resistor to VCC to establish a default condition of a
logical 1 when left floating.
For optimal performance, all data interface digital inputs
should be static when the Edge 629 is actively delaying
signals. (However, it is acceptable if CK continues to run.)
VCC
VCC
CK, SDI, UPDATE
50KΩ
CS
50KΩ
50KΩ
VEE
SEL/SEL*
0
1
Input Source
IN0/IN0* – IN3/IN3*
IN/IN*
Mode
Pass Through
Fanout
Timing Outputs
OUT0/OUT0* – OUT3/OUT3* are standard differential
ECL open emitter outputs.
SEL/SEL* have internal pull-up/pull-down resistors which,
when left floating, place the chip in fanout mode.
VCC
SEL
VCC
SEL*
50KΩ
50KΩ
Compensation Pins
COMP0, COMP1, COMP2, and COMP3 are op amp
compensation pins requiring external 100 pF capacitors
to VEE.
VEE
2005 Semtech Corp. Rev. 3, 8/1/05
10
www.semtech.com
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