FDC37B78X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

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burst before the empty bit needs to be re-read.

Otherwise it may be filled with

writeIntrThreshold bytes.

writeIntrThreshold =

(16-<threshold>) free

bytes in FIFO

An interrupt is generated when serviceIntr is 0

and the number of bytes in the FIFO is less than

or equal to <threshold>. (If the threshold = 12,

then the interrupt is set whenever there are 12 or

less bytes of data in the FIFO.) The PINT pin

can be used for interrupt-driven systems. The

host must respond to the request by writing data

to the FIFO. If at this time the FIFO is empty, it

can be completely filled in a single burst,

otherwise a minimum of (16-<threshold>) bytes

may be written to the FIFO in a single burst.

This process is repeated until the last byte is

transferred into the FIFO.

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