FDC37C666GT View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37C666GT
SMSC -> Microchip
'FDC37C666GT' PDF : 152 Pages View PDF
FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, IDE, serial and
parallel ports can be moved via the
configuration registers. Some addresses are
used to access more than one register.
The host processor communicates with the
FDC37C665GT/666GT through a series of
read/write registers. The port addresses for
these registers are shown in Table 1. Register
access is accomplished through programmed
I/O or DMA transfers. All registers are 8 bits
wide except the IDE data register at port 1F0H
which is 16 bits wide. All host interface output
buffers are capable of sinking a minimum of 24
mA.
Table 1 - FDC37C665GT/666GT Block Addresses
ADDRESS
BLOCK NAME
NOTES
3F0, 3F1
Configuration
Write only; Note 1, 2
3F0, 3F1
Floppy Disk
Read only; Address at power
up; Note 2
3F2, 3F3, 3F4, 3F5, 3F7
Floppy Disk
Address at power up; Note 2
3F8-3FF
Serial Port Com 1 Address at power up; Note 2
2F8-2FF
Serial Port Com 2 Address at power up; Note 2
278-27A
Parallel Port
Address at power up; Note 2
1F0-1F7, 3F6, 3F7
IDE
AT Mode; Note 2, 3
Note 1: Configuration registers can only be modified in configuration mode, entered only by writing a
security code sequence to 3F0. The configuration registers can only be read in configuration
mode by accessing 3F1. Access to status registers A and B of the floppy disk is disabled in
configuration mode. Outside of configuration mode, a read of 3F0 accesses status register A
and a read of 3F1 accesses status register B of the floppy disk.
Note 2: Address at power up; These addresses can be changed in the configuration setup.
Note 3: Addresses 320H-323H and 3F5-3F7H for XT Mode. Selectable in configuration setup.
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