FM3204 View Datasheet(PDF) - Ramtron International Corporation
Part Name
Description
MFG CO.
'FM3204' PDF : 20 Pages View PDF
FM3204/16/64/256
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. All inputs at VSS or VDD, static. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to A0, A1, PFI, or /RST pins.
4. VBAK = 3.0V, VDD < 2.4V, CNT1-2 at VBAK.
5. /RST is asserted low when VDD < VTP.
6. The minimum VDD to guarantee the level of /RST remains a valid VOL level.
7. Full complete operation. Supervisory circuits operate to lower voltages as specified.
8. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM32xx.
9. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications.
10. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max.
AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V, CL = 100 pF unless otherwise specified)
Symbol Parameter
Min Max Min Max Min Max
fSCL
tLOW
tHIGH
tAA
SCL Clock Frequency
Clock Low Period
Clock High Period
SCL Low to SDA Data Out Valid
0 100 0 400 0 1000
4.7
1.3
0.6
4.0
0.6
0.4
3
0.9
0.55
tBUF
Bus Free Before New Transmission 4.7
tHD:STA Start Condition Hold Time
4.0
tSU:STA Start Condition Setup for Repeated 4.7
Start
1.3
0.5
0.6
0.25
0.6
0.25
tHD:DAT Data In Hold Time
0
0
0
tSU:DAT Data In Setup Time
250
100
100
tR
Input Rise Time
1000
300
300
tF
Input Fall Time
300
300
100
tSU:STO Stop Condition Setup Time
4.0
0.6
0.25
tDH
Data Output Hold (from SCL @ VIL) 0
0
0
tSP
Noise Suppression Time Constant
50
50
50
on SCL, SDA
All SCL specifications as well as start and stop conditions apply to both read and write operations.
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
ns
ns
Notes
1
1
Supervisor Timing (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V)
Symbol
Parameter
tRPU
Reset active after VDD>VTP
tRNR
VDD < VTP noise immunity
tVR
VDD Rise Time
tVF
tWDP
tWDOG
fCNT
VDD Fall Time
Pulse Width of /RST for Watchdog Reset
Timeout of Watchdog
Frequency of Event Counters
Data Retention (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V)
Parameter
Min
Data Retention
10
Units
Years
Min
Max Units Notes
100
200
ms
10
25
µs
1
50
-
µs/V
1,2
100
-
µs/V
1,2
100
200
ms
tDOG
2*tDOG
ms
3
0
10
MHz
Notes
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V)
Symbol
Parameter
Max
Units
CIO
Input/output capacitance
8
pF
Notes
1 This parameter is characterized but not tested.
2 Slope measured at any point on VDD waveform.
3 tDOG is the programmed time in register 0Ah, VDD > VTP and tRPU satisfied.
Notes
1
Rev 2.1
Dec. 2004
Page 17 of 20
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