FX029J View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'FX029J' PDF : 6 Pages View PDF
Control Data and Timing
The gain and I/O signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (D0 to
D13). Data is loaded on the rising edge of the Serial Clock. Loaded data is executed on the rising edge of the Load/
Latch pulse.The 14-bit word consists of 1 channel address bit (D7) for selection of the channel to be programmed,
6 bits for setting the amplification/attenuation level (D8-D13), 3 bits for input selection (D4 and D6), and 4 bits for
output settings (D0-D3). This format is illustrated below in Figure 4.
Tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection
and output settings, respectively.
D13 D12 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GAIN/ATTENUATION
LEVEL
INPUT
SELECT
OUTPUT
SETTINGS
Fig.4 Level-Controlling Data Word Format
CHANNEL
ADDRESS
D13 D12 D11 D10 D9 D8
Gain
Set (dB)
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
MUTE
-48
-46
-44
-42
-40
-38
-36
-34
-32
-30
-28
-26
-24
-22
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
Table 1 - Amplification/Attenuation Level
D7
Stage
Selected
D6 D5 D4
0
1
000
1
2
001
010
011
100
101
110
111
Table 2 Stage and Input Selection
Inputs
Selected
none
1
2
1 and 2
3
1 and 3
2 and 3
1, 2 and 3
D13 D12 D11 D10 D9 D8
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
Gain
Set (dB)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
48
48
D3 D2 Output
1B
D1 D0
00
high Z
00
0 1 enabled
01
10
11
VSS
VBIAS
10
11
Table 3 Stage Output Selection
Outputs
1A & 2
high Z
enabled
VSS
VBIAS
4
Share Link: 
