FX589P View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'FX589P' PDF : 18 Pages View PDF
Pin Number
FX589DW
FX589D5
FX589P
Function
1
Xtal: The output of the on-chip clock oscillator.
2
Xtal/Clock: The input to the on-chip Xtal oscillator. A Xtal, or externally derived clock (fXTAL) pulse
input should be connected here. If an externally generated clock is to be used, it should be
connected to this pin and the Xtal pin left unconnected.
Note that operation of the FX589 without a suitable Xtal or clock input may cause device damage.
3
ClkDivA:
Two logic level inputs that control the internal clock divider and hence the transmit and
receive data rate. See Table 1.
4
ClkDivB:
5
Rx Hold: A logic “0” applied to this input will ‘freeze’ the Clock Extraction and Level Measurement
circuits unless they are in ‘acquire’ mode.
6
RXDCacq: A logic “1” applied to this input will set the Rx Level Measurement circuitry to the
‘acquire’ mode.
7
PLLacq: A logic “1” applied to this input will set the Rx Clock Extraction circuitry to ‘acquire’ mode
(see Table 2).
8
Rx PS: A logic “1” applied to this input will powersave all receive circuits except for “Rx Clock”
output (which will continue at the set bit-rate) and cause the “Rx Data” and “Rx S/N” outputs to go
to a logic “0”.
9
V : The internal circuitry bias line, held at V /2, this pin must be decoupled to V by a
BIAS
DD
SS
capacitor mounted close to the pin.
10
Rx Feedback: The output of the Rx Input Amplifier/the input to the Rx Filter.
11
Rx Signal In: The input to Rx Input Amplifier.
12
VSS: Negative supply rail. Signal ground.
2
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