FX641P4 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'FX641P4' PDF : 13 Pages View PDF
Application Information ......
µController
I/O Ports
Ch 2
Ch 1
CLOCK
OUT
CLOCK
IN
XTAL/CLOCK
X1
XTAL
FX641
(used as
Master
Oscillator)
3 to’N’ LINE
DECODER
VDD
"OUTPUT ENABLE"
ADDRESSING
CLOCK
IN
FX641
CLOCK
IN
FX641
CLOCK
IN
FX641
Maximum number of driven clocks (including Master) = 4
Maximum capacitive load on Clock Out output = 15.0pF
Fig.4 Examples of Xtal/Clock Distribution and Output Multiplexing
Xtal/Clock Distribution
The FX641 requires a 3.579545MHz Xtal or clock
pulse input. With the exception of the Xtal, all oscillator
components are incorporated on chip. If a Xtal input is
employed the Clock Out pin should be directly linked to
the Clock In pin.
To reduce component and layout complexity, the
clock requirements of up to 3 additional FX641
microcircuits may be supplied from a Xtal-driven
FX641 acting as the system master clock. With
reference to Figure 4, the clock should be distributed
as illustrated and the Xtal/Clock pins of the driven
microcircuits should be connected directly to VDD.
Note that the maximum load on the master Clock Out
pin should not be exceeded.
Channel Outputs
Channels 1 and 2 outputs operate together under
the control of the Output Enable and Output Select
inputs. Table 3 describes the operations.
The Front Page description describes the output
formats.
SIGNAL INPUT
TONE
NOTONE
Ch1 and Ch 2 OUTPUTS
TONE FOLLOWER OUTPUT
PACKET MODE OUTPUT
SIGNAL INPUT ......
RESPONSE
DELAY
TONE FOLLOWER OUTPUT ......
PACKET MODE OUTPUT ......
Fig.5 Tone Follower and Packet Mode Outputs
DERESPONSE
DELAY
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