FX805LS View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'FX805LS' PDF : 17 Pages View PDF
Timing Information
Timing Diagrams
Figure 9 shows the timing parameters for two-way communication between the µController and the FX805 on the “C-BUS.”
Figure 10 shows, in detail, the timing relationships for “C-BUS” information transfer.
CHIP SELECT
t CSOFF
SERIAL CLOCK
t CSE
COMMAND DATA
76 54 3 2 10
MSB
LSB
REPLY DATA
ADDRESS/COMMAND
BYTE
Logic level is not important
Fig.9 “C-BUS” Timing Information
t NXT
t NXT
t CK
76 54 3 2 10
FIRST DATA BYTE
7 654 3 210
MSB
LSB
FIRST REPLY DATA BYTE
t CSH
7 6543 210
LAST DATA BYTE
7 6543 210
LAST REPLY DATA BYTE
t HIZ
NOT TO SCALE
Parameter
t
CSE
t
CSH
tCSOFF
t
NXT
t
CK
t
CH
t
CL
tCDS
t
CDH
t
RDS
t
RDH
t
HIZ
Min.
2.0
4.0
2.0
4.0
2.0
500
500
250
0
250
50.0
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
–
–
–
–
–
–
–
–
–
2.0
Unit
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
µs
Notes
(1) Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last.
Reply Data is read from the FX805 MSB (bit 7) first, LSB (bit 0) last.
(2) Data is clocked into the FX805 and into the µController on the rising Serial Clock edge.
(3) Loaded data instructions are acted upon at the end of each individual, loaded byte.
(4) To allow for differing µController serial interface formats, the FX805 will work with either polarity Serial
Clock pulses.
t CK
tCL
tCDS
t CH
tCDH
70% VDD
30% VDD
SERIAL CLOCK
(from µC)
COMMAND DATA
(from µC)
REPLY DATA
(to µC)
tRDS
Fig.10 “C-BUS” Timing Relationships
13
tRDH
NOT TO SCALE
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