FX909AD2 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'FX909AD2' PDF : 47 Pages View PDF
Wireless Modem Data Pump
FX909A
The 'Lossy Peak Detect' setting is intended for systems where the µC cannot detect signal fades or
the start of a received message, as it allows the modem to respond quickly to fresh messages and
recover rapidly after a fade without µC intervention - although at the cost of reduced Bit Error Rate
versus Signal to Noise performance.
Note that, since the measured levels are stored on the external capacitors C6 and C7, they will
decay gradually towards VBIAS when the 'Hold' setting is chosen, the discharge time-constant being
approximately 2000 bit times. More details of the level measurement system are given in section
1.6.3.
Control Register B1, B0: PLLBW
These two bits have no effect in transmit mode.
In receive mode, they set the 'normal' bandwidth of the Rx clock extraction Phase Locked Loop
circuit. This setting will be temporarily overridden by the automatic sequencing of an AQBC
command.
B1 B0
00
01
10
11
PLL Bandwidth
Hold
Narrow
Medium
Wide
Suggested use
Signal fades
± 20ppm or better Xtals
Wide tolerance Xtals or long preamble acquisition
Quick acquisition
The 'hold' setting is intended for use during signal fades, otherwise the minimum bandwidth
consistent with the transmit and receive modem bit rate tolerances should be chosen.
The wide and medium bandwidth settings are intended for systems where the µC cannot detect
signal fades or the start of a received message, as they allow the modem to respond rapidly to fresh
messages and recover rapidly after a fade without µC intervention - although at the cost of reduced
Bit Error Rate versus Signal to Noise performance.
Note: More details of the clock extraction system are given in section 1.6.3.
1.5.4.4 Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register B7: IRQNEN - IRQN Output Enable
When this bit is set to '1', the IRQN chip output pin is pulled low (to Vss) whenever the IRQ bit of the
Status Register is a '1'.
© 1996 Consumer Microcircuits Limited
24
D/909A/4
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