GL602USB View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL602USB' PDF : 35 Pages View PDF
Rise Time
CL
Differential
Data Lines
10%
90%
CL
tR
Fall Time
90%
10%
tF
Full Speed: 4 to 20ns at CL = 50pF
Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF
Figure 4-5 Data Signal Rise and Fall Time
4.6.3 Serial Interface Engine (SIE)
The SIE manages data movement between the CPU and the transceiver. The SIE handles both transmit and
receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint
registers.
The byte count buffer is loaded from TXCNT(TXCTL0<3~0>) during endpoint 0 transmit operations. This
same buffer is used for receive transactions to count the number of bytes received at endpoint 0 and, upon
the end of transaction, transfer the value to RXCNT(RXCTL0<3~0>).
When transmitting, the SIE handles parallel-to-serial conversion, CRC generation, NRZI encoding, and bit
stuffing. When receiving, the SIE handles sync detection, packet identification, end-of-packet detection, bit
(un)stuffing, NRZI decoding, CRC validation, and serial-to-parallel conversion. Errors detected by the SIE
include bad CRC, timeout while waiting for EOP, and bit stuffing violations.
All USB devices are required to have an endpoint 0 that is used to initialize and manipulate the device.
Endpoint 0 provides access to the device’s configuration information and allows generic USB status and
control accesses. Endpoint 0 can receive and transmit data. Both receive and transmit data share the same 8-
byte Endpoint 0 FIFO, FFDAT0. Received data may overwrite the data previously in the FIFO.
Transmission from endpoint 0 is controlled by TXCTL0 and receiving from endpoint 0 is controlled by
RXCTL0.
Endpoint 1/endpoint 2/endpoint 3 are of transmit only. Transmission from endpoint 1/endpoint 2/endpoint 3
is controlled by TXCTL123. The target endpoint should be chosen before writing to FFDAT123 and
TXCTL123. There are separated FIFO buffer for the 3 endpoints, but the programming interface for them is
unique, via FFDAT123 register. Size of endpoint 1 FIFO is 8 bytes, endpoint 2 FIFO is 6 bytes, and
endpoint 3 FIFO is 2 bytes.
4.7 INSTRUCTION SET SUMMARY
4.7.1 Operand Field Descriptions
Field
r
A
i
b
Description
Register address
Accumulator
Immediate data
Bit address within a 8-bit register
4.7.2 Instruction Set
Mnemonic,
Operands
Arithmetic Operations
Description
Cycles
Flags
Affected
Revision 1.6
-21-
02/28/2000
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