GL811USB View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL811USB' PDF : 36 Pages View PDF
GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
6.4.3 Ultra DMA data transfer
6.4.3.1 Ultra DMA data burst timing requirements
Name
t2CYCTYP
tCYC
t2CYC
tDS
tDH
tDVS
tDVH
tFS
tLI
tMLI
tUI
tAZ
tZAH
tZAD
tENV
tSR
tRFS
tRP
tIORDYZ
tZIORDY
tACK
tSS
Mode 0
(in ns)
min max
240
112
230
15
5
70
6
0 230
0 150
20
0
10
20
0
20 70
50
75
160
20
0
20
50
Mode 1
(in ns)
min max
160
73
154
10
5
48
6
0 200
0 150
20
0
10
20
0
20 70
30
70
125
20
0
20
50
Mode 2
(in ns)
min max
120
54
115
7
5
30
6
0 170
0 150
20
0
10
20
0
20 70
20
60
100
20
0
20
50
Mode 3
(in ns)
min max
90
39
86
7
5
20
6
0 130
0 100
20
0
10
20
0
20 55
NA
60
100
20
0
20
50
Mode 4
(in ns)
Min max
60
25
57
5
5
6
6
0 120
0 100
20
0
10
20
0
20 55
NA
60
100
20
0
20
50
Comment
Typical sustained average two
cycle time
Cycle time allowing for
asymmetry and clock variations
Two cycle time allowing for clock
variations
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
Data valid hold time at sender
First STORBE time
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for
output drivers to release
Minimum delay time required for
output
Drivers to assert or negate
Envelope time
STROBE to DMARDY_ time
Ready to final STROBE time
Minimum time to assert STOP or
negate DMARQ
Maximum time before releasing
IORDY
Minimum time before driving
STROBE
Setup and hold times for
DMACK_
Time from STROBE edge to
negation of DMARQ or assertion
of STOP
©2000-2002 Genesys Logic Inc.—All rights reserved.
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