GL813 View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL813' PDF : 24 Pages View PDF
GL813 - USB2.0 CompactFlash Card Reader Controller
3.2 Functional Overview
3.2.1 USB 2.0 TXCVR
The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS
signaling.
3.2.2 UTMI Logic
The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles
the low level USB protocol and signaling. The major jobs of UTMI Logic is data and
clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test
modes supporting and serial / parallel conversion.
3.2.3 PLL
40XPLL block will provide 480MHz for USB HS data transmission.
3.2.4 CLKGEN
CLKGEN is the clock generator block for the logic blocks. It generates 15MHz
clock for micro controller, 12MHz for PIO mode, and 30MHz clock for UTMI, SIE,
and FIFO.
3.2.5 CPU
The CPU is the control center of GL813. It’s an 8-bit micro controller operating in
15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command,
then it re-assigns tasks to the CompactFlash controller engine, GPIO, FIFO, and
response proper data/ status to USB host.
3.2.6 CompactFlash Controller Engine
The CompactFlash controller engine is extended from standard ATA/ ATAPI
protocol. It supports PIO mode data transfers.
3.2.7 FIFOs
Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two
sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from
CompactFlash controller engine, and re-direct to USB SIE logic. RXFIFO0 /
RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It
buffers data from USB SIE logic, and re-direct to CompactFlash controller engine.
3.2.8 Control Registers
Control Register configures GL813 to proper operation. For example, CPU can set
register to generate wakeup event, enter suspend, transmits proper USB packet to
host.
©2001-2002 Genesys Logic Inc.—All rights reserved.
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