GL824C View Datasheet(PDF) - GENESYS LOGIC
Part Name
Description
MFG CO.
'GL824C' PDF : 56 Pages View PDF
EXTRST_
RXD
TXD
I2CK
I2CD
VSEL
VBAT
GL824/GL824C USB 2.0 On-The-Go Controller
42
I
(pd)
External reset
117
B
(pu)
UART receives data input
118
O
(pu)
UART transmits data output
120
O
(pu)
I2C bus clock
121
B
(pu)
I2C data
124
I Key voltage detection input
125
I Battery voltage detection input
Pin Name
CS0_
CS1_
DA0~2
AINTRQ
DMACK_
AIORDY
DIOR_
DIOW_
DMARQ
DD0~15
ARESET_
Pin#
43
56
44,46,45
50
51
52
53
54
55
58,60,62,64,
66,68,70,
72,71,69,
67,65,63,
61,59,57
73
Type
O
O
O
I
(pd)
O
I
(pu)
O
O
I
(pd)
ATA/ATAPI Interface
Description
PESETZ (PCVS2Z)
PESETZ (PCVS1Z)
Address 0~2
IREQZ
DMACK
IORDY (WAITZ)
I/O read strobe
I/O write strobe
DMARQ
B
(pd)
Data 0~15
O ARESET
Pin Name
SA1~12
SA0/A0
BA0/WSTS
BA1/RSTS
CKE
RAS_/RE_
Pin#
81,79,77,
78,80,82,
83,86,88,
85,90,91
84
89
87
92
93
Type
SDRAM Interface
Description
O SDRAM_A1~A12
O/I
(pd)
SDRAM_A0 / share pin with A0 pin of HOST interface
SDRAM_BA0 / share pin with write status pin of HOST
interface
O
SDRAM_BA1 / share pin with read status pin of HOST
interface
O SDRAM_CKE
O/I SDRAM_RAS / share pin with read enable pin of HOST
(pu) interface
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