GL827 View Datasheet(PDF) - GENESYS LOGIC
Part Name
Description
MFG CO.
'GL827' PDF : 47 Pages View PDF
GL827 USB 2.0 Single Slot Card Reader Controller
3.3 Pin Descriptions
Table 3.7 - Pin Descriptions
Pin name LQFP100 LQFP48
VDD18O
12
4
GND
AVDD
N/C
DM
DP
RREF
13,14,16,20,21,
27
17,23,24,30
15
18
19
22
5,9,12
6,11
N/A
7
8
10
X1
28
13
X2
29
14
DVDD
31,32,55,56,70,
15,26,35
71
GND
33,34,57,58,68,
16,27,34
69
VP5
51,52
25
VP3
53,54
N/A
PMOSI
72,73
N/A
PMOSO
74,75
36
TEST_MOD
35
17
EXTRSTZ
36
18
EAB
94
N/A
SM_CDZ
6
2
SSOP28 QFN24
N/A
N/A
6
N/A
7
1,5
N/A
N/A
9
2
8
3
10
4
4
6
5
7
3,,11 8,14,17
6
24
12
13
N/A
N/A
N/A
N/A
2
18
N/A
N/A
13
9
N/A
N/A
N/A
N/A
QFN24
N/A
N/A
2,6
N/A
3
4
5
7
8
9,14,17
1
13
N/A
N/A
18
N/A
10
N/A
N/A
CSP23
N/A
Type
Description
Internal regulator 1.8V
P
output
F4,H4
P Analog ground
E5
P Analog power
N/A
A Test only
D4
A USB D-
G5
A USB D+
E3
A Reference resistor
12MHz/48MHz input.
This pin can be connected
J5
OSC to one terminal of crystal
or external
12MHz/48MHz clock
source.
12MHz/48MHz output.
This is another terminal of
the crystal or NC when
G3
OSC using an external
12MHz/48MHz clock
source is used to drive
PLL.
D2
P Digital power 3.3V
G1
P Digital ground
F2
P Regulator 5V Input
N/A
P Regulator 3.3V output
N/A PMOS Power MOS 3.3V input
B2 PMOS Power MOS 3.3V output
N/A
I, pd Test mode selection
External reset. It is active
J3
I, pu low. The low pulse should
be 1 us width at least.
N/A B/I, pu Ext flash selection
N/A B/I, pd SmartMedia Card
detection. Normal High,
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