GL827S-OHG View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL827S-OHG' PDF : 21 Pages View PDF
GL827S USB 2.0 Single Slot Card Reader Controller
CHAPTER 6 FUNCTION DESCRIPTION
UTM
The USB 2.0 Transceiver Macrocell is the analog circuitry that handles the low level USB protocol and signaling,
and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic.
SIE
The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing
and state machine logic to handle USB packets and transactions.
EPFIFO
Endpoint FIFO includes Control FIFO (FIFO0), interrupt FIFO (FIFO3), Bulk In/Out FIFO (BULKFIFO)
Control FIFO
FIFO of control endpoint 0.
It is 64-byte FIFO, and it is used for endpoint 0 data transfer.
Interrupt FIFO 64-byte depth FIFO of endpoint 3 for status interrupt
Bulk In/Out FIFO It can be in the TX mode or RX mode:
1. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously.
2. It can be directly accessed by Uc
MHE
It contains 3 MIFs (Media Interface)
MIFs
1. SD / MMC
2. MemoryStick/ MemoryStick PRO / MemoryStick PRO-HG
3. xD-Picture
External reset circuit
Non-inverting, Schmitt input with weak pull-up using DVDD power.
©2009 Genesys Logic Inc. - All rights reserved.
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