GL830 View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL830' PDF : 29 Pages View PDF
GL830 USB2.0 to SATA Bridge Controller
CHAPTER 5 FUNCTION DESCRIPTION
5.1 UTM
The USB 2.0 Transceiver Macrocell, it’s the analog circuitry that handles the low level USB protocol and
signaling, and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the
general logic.
5.2 SIE
The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing
and state machine logic to handle USB packets and transactions.
5.3 EP0/EP3 FIFO and Bulk Buffer
Endpoint 0/3 FIFO: The Control and Interrupt FIFO. It is composed of TX03FIFO and RX03FIFO, with
64-byte FIFO each, and it is used for endpoint 0/3 data transfer.
Bulk Buffer: It is constructed in interleaved architecture and composed by two data buffers which is used to store
data transferred between USB host and IDE device.
5.4 Operation Register
It is a register space to store status information and to control the functions of GL830 by 8051.
5.5 SPI Interface
The Serial Peripheral Interface is a serial, synchronous communication protocol. It is compatible with
Motorola’s SPI specifications.
5.6 PHY Layer
It has elastic buffer and supports receiver detection, data serialization and de-serialization.
5.7 Link Layer
The Link layer transmits and receives frames, transmits primitives based on control signals from the Transport
layer, and receives primitives from the Phy layer which are converted to control signals to the Transport layer.
5.8 Transport Layer
The Transport layer constructs Frame Information Structures for transmission and decomposes received Frame
Information Structure
5.9 Application Layer
The Application Layer translates the ATA operation onto internal protocols.
©2007 Genesys Logic Inc. - All rights reserved.
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