GMS97C8HPL View Datasheet(PDF) - Hynix Semiconductor
Part Name
Description
MFG CO.
'GMS97C8HPL' PDF : 59 Pages View PDF
GMS90 Series
TIMER / COUNTER 0 AND 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
Table 4. Timer/Counter 0 and 1 Operating Modes
Mode
0
1
2
3
Description
8-bit timer/counter with a
divide-by-32 prescaler
16-bit timer/counter
8-bit timer/counter with
8-bit auto-reload
Timer/counter 0 used as
one 8-bit timer/counter and
one 8-bit timer Timer 1
stops
Gate
X
X
X
X
TMOD
C/T M1
X
0
X
0
X
1
X
1
Input Clock
M0
internal
external (Max.)
0 fOSC ÷(12×32) fOSC ÷(24×32)
1
fOSC ÷12
fOSC ÷24
0
fOSC ÷12
fOSC ÷24
1
fOSC ÷12
fOSC ÷24
In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is
fOSC/12.
In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding exter-
nal input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate
is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate
pulse width measurements. Figure 2 illustrates the input clock logic.
fOSC
÷ 12
P3.4/T0
P3.5/T1
Max. fOSC/24
TR0 / 1
TCON
Gate
=1
TMOD
P3.2 / INT0
P3.3 / INT1
C/T
TMOD
0
1
&
≥1
Figure 2. Timer/Counter 0 and 1 Input Clock Logic
Oct. 2000 Ver 3.1a
fOSC ÷ 12
Timer 0/1
Input Clock
19
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