HCPL-2503-360E View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'HCPL-2503-360E' PDF : 12 Pages View PDF
Recommended Circuit Design Parameters
Parameter
Symbol
LSTTL-to-
LSTTL
Input
Logic Low Output
Voltage – Input Gate
VOL (A) 0.5
Supply Voltage – Input
VCC1
5.0
Input Resistor
RIN
360
430
Input Current
IF
8
Input Current Range
IF
6.75–10
Output
Logic Low Output
Voltage – HCPL-2503
VOL (B) 0.5
Supply Voltage – Output VCC2
5.0
Pull-Up Resistor
RL
20
Required Current Sink
for Logic Low
IOL
0.61
(max)
HCPL-2503 Current
Transfer Ratio
CTR
11
Logic Low Output
Current – HCPL-2503
IOL
0.74
(min)
Data Rate
fD
250
TTL-to-
LSTTL Units
Comments
Fig. Note
0.4
V
Maximum
5.0
V
± 5%
180
Ω
± 5%
8a
200
8b
16
mA
Nominal
14.0–20 mA
8a
14.5–20
8b
0.5
V
Maximum
5.0
V
± 5%
8.2
kΩ
± 5%
11
1.0
mA
Worst Case VCC,
12
RL, IIL (B)
9
%
Minimum TA = 0˚C to
+70°C
1.26
mA
1.30
Worst Case VCC, CTR, IF
TA = 0°C to +70°C
8a 13
8b
250
kb/s
NRZ, TA = 25°C
14
Notes:
10. The inverting circuit has higher power consumption and must use open collector gates on the input.
11. The load resistor RL must be large enough to guarantee logic LOW and small enough to guarantee logic HIGH under worst case conditions:
VCC (max) – VOL
IOL (2503) – IIL (B)
≤ RL ≤
VCC (min) – VIH (B)
IOH (2503) – IIH (B)
The selection of RL is the same for both inverting and non-inverting circuits.
12. The maximum current sink required for logic LOW is:
IOL (max) = IIL (B) (max) + IR (max)
where IR is the current through RL.
13. The ratio of IOL (min) to IOL (max) gives the design margin for CTR degradation. See Application Note 1002.
14. The maximum data rate is defined as:
fD = t P H L 1 + t P L H bits/second NRZ
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.
AV02-0520EN - June 15, 2007
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