HCPL-3150-360 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'HCPL-3150-360' PDF : 21 Pages View PDF
IPM Dead Time and Propagation Delay Specifications
The HCPL-3150/315J includes a Propagation Delay Dif-
ference (PDD) specification intended to help designers
minimize “dead time” in their power inverter designs.
Dead time is the time period during which both the high
and low side power transistors (Q1 and Q2 in Figure 25)
are off. Any overlap in Q1 and Q2 conduction will result
in large currents flowing through the power devices
from the high- to the low-voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has
just turned off when transistor Q2 turns on, as shown in
Figure 34. The amount of delay necessary to achieve this
conditions is equal to the maximum value of the propa-
gation delay difference specification, PDD , which is
MAX
specified to be 350 ns over the operating temperature
range of -40°C to 100°C.
Delaying the LED signal by the maximum propaga-
tion delay difference ensures that the minimum dead
time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead
time is equivalent to the difference between the
maximum and minimum propagation delay differ-
ence specifications as shown in Figure 35. The maxi-
mum dead time for the HCPL-3150/315J is 700 ns
(= 350 ns - (-350 ns)) over an operating temperature
range of -40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other
and are switching identical IGBTs.
1
8
CLEDP
2
7
3
6
CLEDN
4
5
Figure 29. Optocoupler Input to Output Capacitance Model for
Unshielded Optocouplers.
1
CLEDO1
8
CLEDP
2
7
CLEDO2
3
6
CLEDN
4
5
SHIELD
Figure 30. Optocoupler Input to Output Capacitance Model for
Shielded Optocouplers.
+5 V
+
VSAT
–
1
CLEDP
2
ILEDP
3
CLEDN
4
SHIELD
8
0.1
7
μF
+
–
VCC = 18 V
6
•••
Rg
5
•••
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
+–
VCM
Figure 31. Equivalent Circuit for Figure 25 During Common Mode Transient.
19
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