1
8
IF = 7 to 16 mA
2
7
+ 500 Ω
10 KHz –
50% DUTY
3
6
CYCLE
4
5
Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
0.1 μF
+
–
VCC = 15
to 30 V
VO
47 Ω
3 nF
IF
tr
VOUT
tPLH
1
8
IF
A
B
2
7
5V
+
–
3
6
4
5
+
VCM = 1500 V
Figure 24. CMR Test Circuit and Waveforms.
VCM
0.1 μF
VO
+
–
VCC = 30 V
0V
Δt
VO
SWITCH AT A: IF = 10 mA
VO
SWITCH AT B: IF = 0 mA
tf
90%
50%
10%
tPHL
δV = VCM
δt Δt
VOH
VOL
Applications Information
Eliminating Negative IGBT Gate Drive
To keep the IGBT firmly off, the HCPL-3150/315J has a
very low maximum V specification of 1.0V. The HCPL-
OL
3150/315J realizes this very low V by using a DMOS
OL
transistor with 4 Ω (typical) on resistance in its pull down
circuit. When the HCPL-3150/315J is in the low state, the
IGBT gate is shorted to the emitter by Rg + 4 Ω. Minimiz-
ing Rg and the lead inductance from the HCPL-3150/315J
to the IGBT gate and emitter (possibly by mounting the
HCPL-3150/315J on a small PC board directly above the
IGBT) can eliminate the need for negative IGBT gate drive
in many applications as shown in Figure 25. Care should
be taken with such a PC board design to avoid routing
the IGBT collector or emitter traces close to the HCPL-
3150/315J input as this can result in unwanted coupling
of transient signals into the HCPL-3150/315J and de-
grade performance. (If the IGBT drain must be routed
near the HCPL-3150/315J input, then the LED should be
reverse-biased when in the off state, to prevent the tran-
sient signals coupled from the IGBT drain from turning
on the HCPL-3150/315J.)
+5 V
1
270 Ω
2
CONTROL
INPUT
3
74XXX
OPEN
4
COLLECTOR
HCPL-3150
8
0.1 μF
7
6
5
Figure 25a. Recommended LED Drive and Application Circuit.
+ VCC = 18 V
–
Rg
Q1
Q2
13
+ HVDC
3-PHASE
AC
- HVDC