HCPL-7710-360E View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'HCPL-7710-360E' PDF : 17 Pages View PDF
HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in either an 8-pin DIP or SO-8 package style • +5 V CMOS compatibility
respectively, the HCPL-7710 or HCPL-0710 optocouplers • 8 ns maximum pulse width distortion
utilize the latest CMOS IC technology to achieve out-
standing performance with very low power consump-
tion. The HCPL-x710 require only two bypass capacitors
for complete CMOS compatibility.
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
Basic building blocks of the HCPL-x710 are a CMOS • 10 kV/µs minimum common mode rejection
LED driver IC, a high speed LED and a CMOS detector • -40°C to 100°C temperature range
IC. A CMOS logic input signal controls the LED driver • Safety and regulatory approvals
IC, which supplies current to the LED. The detector IC UL Recognized
incorporates an integrated photodiode, a high-speed
transimpedance amplifier, and a voltage comparator
with an output driver.
3750 Vrms for 1 min. per UL 1577
5000 Vrms for 1 min. per UL 1577 (for HCPL-7710
option 020)
Functional Diagram
CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-5
**VDD1 1
8 VDD2**
(PTORSUITTIHVETAL––OBVVLGEIIIOOCRR)MM
=
=
630
567
Vpeak
Vpeak
for
for
HCPL-7710
HCPL-0710
Option
Option
060
060
VI, INPUT LED1 VO, OUTPUT
VI 2
7 NC*
H
OFF
H
L
OANpplicatioLns
NC* 3
GND1 4
LED1
SHIELD
IO
6 VO
5 GND2
• Digital fieldbus isolation: DeviceNet, SDS, Profibus
• AC plasma display panel level shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
8 VDD2**
7 NC*
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
IO
6 VO
5 GND2
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
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