HCS12COREUG View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
MFG CO.
'HCS12COREUG' PDF : 124 Pages View PDF
MC9S12H256 Device User Guide — V01.14
2.3.3 TEST — Test Pin
This pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter.
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
2.3.6 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]
PAD15-PAD8 are general purpose input pins and analog inputs for the analog to digital converter.
NOTE: These pins are not available in the 112-pin LQFP version.
2.3.7 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]
PAD7-PAD0 are general purpose input pins and analog inputs for the analog to digital converter.
2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP15-FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
2.3.9 PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP7-FP0 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7
PE7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP22
of the LCD module. The XCLKS signal selects between an external clock or oscillator configuration
during reset.
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