HD404324FS View Datasheet(PDF) - Hitachi -> Renesas Electronics
Part Name
Description
MFG CO.
'HD404324FS' PDF : 94 Pages View PDF
HD404328 Series
Write operations are valid from the second instruction execution cycle, so the STS instruction must be
executed after at least two cycles have been executed. The serial mode register is initialized to $0 by MCU
reset.
Serial mode register (SMR): $005
3
2
1
0
Initial value: 0000,
R/W: W
Transmit clock selection
R10 /SCK pin mode selection
SMR
Bit 3
0
1
R10 /SCK Pin
R10 port input or output pin
SCK input or output pin
SMR
R10/SCK Pin Clock Source
Bit 2 Bit 1 Bit 0
Prescaler Division
Ratio
Transmit Clock
Period
0
0 0 SCK output Prescaler
÷ 2048
4096 tcyc
1 SCK output Prescaler
÷ 512
1024 tcyc
1 0 SCK output Prescaler
÷ 128
256 tcyc
1 SCK output Prescaler
÷ 32
64 tcyc
1
0
0 SCK output Prescaler
÷8
16 tcyc
1 SCK output Prescaler
÷2
1 0 SCK output System clock —
4 tcyc
1 tcyc
1 SCK input
External clock —
—
Note: tcyc = 1.9074 µs (with 4.1943-MHz crystal oscillator used at 1/8 division ratio)
Figure 30 Serial Mode Register
Serial Data Register (SRL: $006, SRU: $007): Eight-bit read/write register separated into upper and
lower digits located at sequential addresses. Data in this register is output from the SO pin, LSB first, in
synchronism with the falling edge of the transmit clock; and data is input, LSB first, through the SI pin at
the rising edge of the transmit clock. Input/output timing is shown in figure 31.
Data cannot be read or written during serial data transmission. If a read/write occurs during transmission,
the accuracy of the resultant data cannot be guaranteed.
52
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