HD404324UFS View Datasheet(PDF) - Hitachi -> Renesas Electronics
Part Name
Description
MFG CO.
'HD404324UFS' PDF : 94 Pages View PDF
Transmission
completion (IFS ← 1)
Interrupts inhibited
HD404328 Series
IFS ← 0
SMR write
Yes
IFS = 1?
No
Normal termination
Transmit clock
error processing
Figure 33 Transmit Clock Error Detection
Note on Use: The serial interrupt request flag might not be set if the status is changed from transfer by the
execution of an SMR write or STS instruction during the first period that the transmit clock is low. To
prevent this, program a check that the SCK pin is at 1 (by executing an input instruction for the R1 port)
before the execution of an SMR write or STS instruction, to ensure that the serial interrupt request flag is
set.
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