HD61202UFS View Datasheet(PDF) - Hitachi -> Renesas Electronics
Part Name
Description
MFG CO.
'HD61202UFS' PDF : 33 Pages View PDF
HD61202U
2. Example of Connection with HD6801
• Set HD6801 to mode 5. P10 to P14 are used as the output port and P30 to P37 as the data bus.
• 74LS154 4-to-16 decoder generates chip select signal to make specified HD61202U active after
decoding 4 bits of P10 to P13.
• Therefore, after enabling the operation by P10 to P13 and specifying D/I signal by P14, read/write
from/to the external memory area ($0100 to $01FE) to control HD61202U. In this case, IOS signal is
output from SC1 and R/W signal from SC2.
• For details of HD6800 and HD6801, refer to their manuals.
P10
P11
P12
P13
(IOS) (SC1)
(R/W) (SC2)
HD6801 P14
E
P30
(Data bus)
P37
74LS154
A Y0
B Y1
C
D Y15
G1 G2
CS1
CS2
VCC CS3
R/W
D/I HD61202U
No. 1
E
DB0
DB7
Figure 8 Examples of Connection with HD6801
839
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