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HD6433024F View Datasheet(PDF) - Hitachi -> Renesas Electronics

Part Name
Description
MFG CO.
HD6433024F
Hitachi
Hitachi -> Renesas Electronics Hitachi
'HD6433024F' PDF : 824 Pages View PDF
Before Execution of BCLR Instruction
Input/output
DDR
P47
Input
0
P46
Input
0
P45
Output
1
P44
Output
1
P43
Output
1
P42
Output
1
P41
Output
1
P40
Output
1
Execution of BCLR Instruction
BCLR #0, P4DDR ; Execute BCLR instruction on DDR
After Execution of BCLR Instruction
Input/output
DDR
P47
Output
1
P46
Output
1
P45
Output
1
P44
Output
1
P43
Output
1
P42
Output
1
P41
Output
1
P40
Input
0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47 and P46 output pins.
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the
IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when
using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling
routine, for instance, it is not necessary to read the flag ahead of time.
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