HD6433024FP View Datasheet(PDF) - Hitachi -> Renesas Electronics
Part Name
Description
MFG CO.
'HD6433024FP' PDF : 824 Pages View PDF
Table 1.1 Features
Feature
CPU
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
High-speed operation
H8/3024F-ZTAT
H8/3026F-ZTAT
H8/3024 (mask ROM version)
H8/3026 (mask ROM version)
Maximum
clock rate
25 MHz
Add/
subtract
80 ns
Multiply/
divide
560 ns
Memory
16-Mbyte address space
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
ROM
RAM
H8/3024F-ZTAT
128 kbytes 4 kbytes
H8/3024 (mask ROM version)
H8/3026F-ZTAT
256 kbytes 8 kbytes
H8/3026 (mask ROM version)
Interrupt
controller
• Seven external interrupt pins: NMI, IRQ0 to IRQ5
• 27 internal interrupts
• Three selectable interrupt priority levels
2
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