HD6433024FP View Datasheet(PDF) - Hitachi -> Renesas Electronics
Part Name
Description
MFG CO.
'HD6433024FP' PDF : 824 Pages View PDF
Type
System
control
Symbol
RES
RESO
FWE
STBY
BREQ
BACK
Interrupts NMI
Address
bus
IRQ5 to
IRQ0
A23 to A0
Data bus D15 to D0
Bus
control
CS7 to
CS0
AS
RD
HWR
LWR
WAIT
Pin No.
FP-100B
TFP-100B FP-100A I/O
Name and Function
63
65
Input Reset input: When driven low, this pin resets
the chip. This pin must be driven low at power-
up.
10
12
Output Reset output (On-chip mask ROM
versions): Outputs the reset signal generated
by the watchdog timer to external devices
10
12
Input Write enable signal (On-chip flash memory
versions): Flash memory programming
control signal
62
64
Input Standby: When driven low, this pin forces
a transition to hardware standby mode
59
61
Input Bus request: Used by an external bus master
to request the bus right
60
62
Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus
master
64
66
Input Nonmaskable interrupt: Requests a
nonmaskable interrupt
17, 16, 19, 18, Input Interrupt request 5 to 0: Maskable interrupt
90 to 87 92 to 89
request pins
97 to 100, 99, 100, Output Address bus: Outputs address signals
56 to 45, 1, 2,
43 to 36 58 to 47,
45 to 38
34 to 23, 36 to 25, Input/ Data bus: Bidirectional data bus
21 to 18 23 to 20 output
2 to 5, 4 to 7, Output Chip select: Select signals for areas 7 to 0
88 to 91 90 to 93
69
71
Output Address strobe: Goes low to indicate valid
address output on the address bus
70
72
Output Read: Goes low to indicate reading from the
external address space
71
73
Output High write: Goes low to indicate writing to the
external address space; indicates valid data
on the upper data bus (D15 to D8).
72
74
Output Low write: Goes low to indicate writing to the
external address space; indicates valid data
on the lower data bus (D7 to D0).
58
60
Input Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
11
Share Link: 
