HDNS-2200 View Datasheet(PDF) - Agilent Technologies, Inc
Part Name
Description
MFG CO.
'HDNS-2200' PDF : 36 Pages View PDF
Two Solutions
There are two different ways to
solve the problem: (1) waiting for
the serial port watchdog timer to
time out, or (2) using the PD line
to reset the serial port.
supply. If not, then the micropro-
cessor must wait tSPTT from
ADNS-2030 VDD valid. Then when
the SCLK toggles for the address,
the ADNS-2030 will be in sync
with the microprocessor.
1. Serial port watchdog timer timeout
(Refer to Figure 35.)
If the microprocessor waits at
least tSPTT from VDD valid, it will
ensure that the ADNS-2030 has
powered up and the watchdog
timer has timed out. This assumes
that the microprocessor and the
ADNS-2030 share the same power
2. PD Sync
(Refer to Figure 36.)
The PD line can be used to
resync the serial port. If the
microprocessor waits for 4 ms
from VDD valid, and then outputs
a valid PD pulse (Refer to Figure
14), then the serial port will be
ready for data.
Resync Note
If the microprocessor and the
ADNS-2030 get out of sync, then
the data either written or read
from the registers will be incor-
rect. An easy way to solve this is
to output a PD pulse to resync
the parts after an incorrect read.
VDD
>t SPTT
PD
SCLK
SDIO
Address = 0x00
Figure 35. Power up serial port watchdog timer sequence.
4 ms
VDD
PD
SCLK
SDIO
Address =0x00
Figure 36. Power up serial port PD sync sequence.
Data = 0x03
Data =0x03
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