HDNS-2200 View Datasheet(PDF) - Agilent Technologies, Inc
Part Name
Description
MFG CO.
'HDNS-2200' PDF : 36 Pages View PDF
Recommended Operating Conditions
Parameter
Symbol
Operating Temperature
Power Supply Voltage
Power Supply Rise Time
Supply Noise
Clock Frequency
Serial Port Clock Frequency
Resonator Impedance
Distance from Lens Reference
Plane to Surface
Speed
Acceleration
Light Level onto IC
TA
VDD
VRT
VN
fCLK
SCLK
XRES
Z
S
A
IRRINC
SDIO Read Hold Time
tHOLD
SDIO Serial Write-write Time
tSWW
SDIO Serial Write-read Time
tSWR
SDIO Serial Read-write Time
tSRW
SDIO Serial Read-read Time
tSRR
Data Delay after PD
tCOMPUTE
SDIO Write Setup Time
PD Pulse Width
(to power down the chip)
PD Pulse Width
(to reset the serial port)
Frame Rate
Bin Resistor
tSETUP
tPDW
tPD
FR
R1
Minimum
0
3.0
Typical
3.3
17.4
18.0
2.3
2.4
0
80
100
100
100
100
120
120
3.2
60
700
100
1500
15K
15K
Maximum
40
3.6
100
30
18.7
fCLK/4
55
2.5
14
0.15
25,000
30,000
37K
Units Notes
°C
Volts
ms
mV
MHz
MHz
Ω
mm
in/sec
g
mW/m2
µs
µs
µs
ns
ns
ms
ns
µs
µs
frames/s
Ω
Peak to peak @27 MHz bandwidth
Set by ceramic resonator
Results in ±0.2 mm DOF
(See Figure 9.)
@ frame rate = 1500 fps
@ frame rate = 1500 fps
λ = 639 nm
λ = 875 nm
Hold time for valid data
(Refer to Figure 27.)
Time between two write commands
(Refer to Figure 30.)
Time between write and read
operation (Refer to Figure 31.)
Time between read and write
operation (Refer to Figure 32.)
Time between two read commands
(Refer to Figure 32.)
After tCOMPUTE, all registers contain
data from first image after PD . Note
that an additional 75 frames for AGC
stabilization may be required if mouse
movement occurred while PD was
high. (Refer to Figure 11.)
Data valid time before the rising of
SCLK (Refer to Figure 25.)
Pulse width to initiate the power down
cycle @1500 fps (Refer to Figure 13.)
Pulse width to reset the serial port
@1500 fps (but may also initiate a
power down cycle) (Refer to Figure 11.)
See Frame_Period register section
Refer to Figure 8
7
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