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HDSP-2131 View Datasheet(PDF) - HP => Agilent Technologies

Part Name
Description
MFG CO.
'HDSP-2131' PDF : 16 Pages View PDF
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UDC RAM and UDC Address
Register
Figure 3 shows the logic levels
needed to access the UDC RAM
and the UDC Address Register.
The UDC Address Register is
eight bits wide. The lower four
bits (D0-D3) are used to select
one of the 16 UDC locations. The
upper four bits (D4-D7) are not
used. Once the UDC address has
been stored in the UDC Address
Register, the UDC RAM can be
accessed.
To completely specify a 5 x 7
character requires eight write
cycles. One cycle is used to store
the UDC RAM address in the UDC
Address Register. Seven cycles
are used to store dot data in the
UDC RAM. Data is entered by
rows. One cycle is needed to
access each row. Figure 4 shows
the organization of a UDC
character assuming the symbol to
be stored is an “F.” A0-A2 are used
to select the row to be accessed
and D0-D4 are used to transmit
the row dot data. The upper three
bits (D5-D7) are ignored. D0
(least significant bit) corresponds
to the right most column of the 5
x 7 matrix and D4 (most
significant bit) corresponds to
the left most column of the 5 x 7
matrix.
Figure 3. Logic Levels to Access a UDC Character.
Flash RAM
Figure 5 shows the logic levels
needed to access the Flash RAM.
The Flash RAM has one bit
associated with each location of
the Character RAM. The Flash
input is used to select the Flash
RAM. Address lines A3-A4 are
ignored. Address lines A0-A2 are
used to select the location in the
Flash RAM to store the attribute.
D0 is used to store or remove the
flash attribute. D0 = “1” stores
the attribute and D0 = “0”
removes the attribute.
Figure 4. Data to Load “F” into the UDC RAM.
When the attribute is enabled
through bit 3 of the Control Word
and a "1" is stored in the Flash
RAM, the corresponding character
will flash at approximately 2 Hz.
The actual rate is dependent on
the clock frequency. For an
external clock the flash rate can
be calculated by dividing the
clock frequency by 28,672.
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