HI-3200PCTF View Datasheet(PDF) - Holt Integrated Circuits
Part Name
Description
MFG CO.
'HI-3200PCTF' PDF : 59 Pages View PDF
HI-3200, HI-3201
HI-3200 SYSTEM CONFIGURATION
Starting at memory address 0x8000, the HI-3200
contains a set of registers that are used to configure the
HI-3200 device and, if used, its associated HI-3110
integrated CAN controller / transceiver.
The user needs only to program the HI-3200
configuration registers to completely define the full
system operation.
Configuration information for the HI-3110 is automatically
transferred from the HI-3200 to the HI-3110 immediately
after the RUN input is asserted.
An SPI by-pass mode allows the user to directly access
the HI-3110, but it is highly recommended that this is
used solely for design debugging purposes and is locked
out in the final design implementation. By-pass mode is
enabled by setting the state of the MODE2:0 pins during
reset. See the Reset and Start-Up Configuration section
for more details.
The configuration registers are divided into four
categories, as follows;
1. HI-3200 global configuration
2. ARINC 429 Receive channel configuration
3. ARINC 429 Transmit channel configuration
4. CAN Bus bit timing configuration
HI-3200 Global Configuration
The following registers define the HI-3200 top-level configuration:
A429RAX429TCXANRCXANTAXFLIP
MASTER CONTROL REGISTER
(Address 0x800F)
XXX
76543210
MSB
LSB
Bit Name
R/W Default Description
7 A429RX
R/W 0 This bit must be set to a “1” to allow the HI-3200 to receive ARINC 429 data on any of the eight
channels. If set to a zero, the HI-3200 will not respond to any ARINC 429 receive bus,
regardless of the state of the ARINC 429 Receive channel Control Registers.
6 A429TX
R/W 0 This bit must be set to a “1” to allow the HI-3200 to transmit ARINC 429 data on any of the four
channels. If set to a zero, the HI-3200 will not output ARINC 429 data and the ARINC 429
transmit sequencers will remain in their reset state.
5 CANRX
R/W 0 This bit must be set to a “1” to allow the HI-3200 to receive CAN Frames from the HI-3110
controller. If set to a zero, the HI-3200 will not respond to any received CAN frames, regardless
of the state of the CAN Bus Control Register.
4 CANTX
R/W 0 This bit must be set to a “1” to allow the HI-3200 to transmit CAN frames. If set to a zero, the
HI-3200 will not output CAN frames and the CAN transmit sequencer will remain in its reset
state.
3 AFLIP
R/W 0 When set to a “1”, this bit switches the bit order of the ARINC 429 label byte in both receive and
transmit channels.
2-
R/W 0 Not Used
1-
R/W 0 Not Used
0-
R/W 0 Not Used
HOLT INTEGRATED CIRCUITS
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