HM628128DLPI-7 View Datasheet(PDF) - Hitachi -> Renesas Electronics
Part Name
Description
MFG CO.
'HM628128DLPI-7' PDF : 16 Pages View PDF
HM628128DI Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol Min Typ*3 Max Unit Test conditions*2
VCC for data retention
VDR
2.0 —
—V
Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V
CS1 ≥ VCC – 0.2 V
Data retention current
I
*1
CCDR
—
1.0 50
µA
VCC = 3.0 V, Vin ≥ 0 V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V,
CS1 ≥ VCC – 0.2 V
Chip deselect to data retention time tCDR
0
—
— ns
See retention waveform
Operation recovery time
tR
tRC*4 —
— ns
Notes: 1. This characteristic is guaranteed only for L-version, 30 µA max. at Ta = –40 to +40°C.
2. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If
CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
3. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
4. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
tCDR
Data retention mode
tR
VCC
4.5 V
2.4 V
VDR
CS1
0V
CS1 ≥ VCC – 0.2 V
12
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