HT47C20L View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT47C20L' PDF : 55 Pages View PDF
Example for RC type AD converter mode (Timer B overflow):
clr tmrc
clr adcr.1
; set timer mode
clr intc1.4
; clear timer/event counter interrupt request flag
a, 00h
; give timer A initial value
mov tmrbl, a
a, 00h
mov tmrbh, a
HT47C20L
mov a, 00010011b
mov adcr,a
; RS0~CS0; set RC type ADC mode; set Timer B overflow
mov a, low (65536-1000)
mov tmrbl, a
mov a, high (65536-1000)
mov tmrbh, a
; give timer B initial value
; count 1000 time and then overflow
mov a, 00110000b
mov tmrc, a
; timer A clock source=T1 and timer on
p10:
clr wdt
snz intcl.4
jmp p10
; polling timer/event counter interrupt request flag
clr intcl.4
; clear timer/event counter interrupt request flag
; program continue
Input/Output Ports
There are 8-bit bidirectional input/output port and 4-bit
input port in the HT47C20L, labeled PA and PB which
are mapped to the data memory of [12H] and [14H] re-
spectively. The high nibble of the PA is NMOS output
and input with pull-high resistors. The low nibble of the
PA can be used for input/output or output operation by
selecting NMOS or CMOS output by mask option. Each
bit on the PA can be configured as a wake-up input and
the low nibble of the PA with or without pull-high resis-
tors by mask option. PB can only be used for input oper-
ation, and each bit on the port is with pull high resistor.
Both are for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA output operation, all data are latched and
remain unchanged until the output latch is rewritten.
When the structures of PA are open drain NMOS type, it
should be noted that, before reading data from the pads a
²1² should be written to the related bits to disable the
NMOS device. That is done first before executing the in-
struction ²MOV A, 0FFH² and ²MOV [12H], A² to disable
the related NMOS device, and then ²MOV A, [12H]² to get
a stable data.
After chip reset, these input lines remain at a high level
or are left floating (by mask option).
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m].i²,
²CPL [m]², ²CPLA [m]² read the entire port states into the
CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator. Each bit of the PA output latches can not
use these instruction, which may change the input lines
to output lines (when the input lines are at low level).
Rev. 2.30
21
December 2, 2005
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