HT48C10 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48C10' PDF : 59 Pages View PDF
HT48CXX/HT48RXX
Mnemonic
Description
Flag Affected
Instruction
Cycle
Miscellaneous
NOP
CLR [m]
SET [m]
No operation
Clear data memory
Set data memory
None
1
None
1(1)
None
1(1)
CLR WDT
Clear Watchdog timer
TO,PD
1
CLR WDT1 Pre-clear Watchdog timer
TO*,PD*
1
CLR WDT2
SWAP [m]
Pre-clear Watchdog timer
Swap nibbles of data memory
TO*,PD*
1
None
1(1)
SWAPA [m] Swap nibbles of data memory with result in ACC
None
1
HALT
Enter power down mode
TO,PD
1
Notes: x: 8-bit immediate data
m: 7-bit data memory address for HT48C10/HT48C30
m: 8-bit data memory address for HT48C50/HT48C70
A: Accumulator
i: 0~7 number of bits
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
√: Flag(s) is affected
–: Flag(s) is not affected
*: Flag(s) may be affected by the execution status
(1): If a loading to PCL register occurs, the execution cycle of the instructions will be delayed
one more cycle (4 system clocks).
(2): If a skip to next instruction occurs, the execution cycle of instructions will be delayed one
more cycle (4 system clocks). Otherwise the original execution cycles remain unchanged.
(3) : (1) or (2)
31
25th May ’99
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