HT48CA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48CA1' PDF : 39 Pages View PDF
HT48RA1/HT48CA1
After a chip reset, these input/output lines stay at high
levels (pull-high options) or floating state (non-pull-high
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² (m=12H, 14H, 16H or 1CH)
instructions. Some instructions first input data and then
follow the output operations. For example, ²SET [m].i²,
²CLR [m].i², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or the ac-
cumulator.
Each line of port A has the capability of waking-up the
device. The highest 2 bits of port C and 7 bits of port F
are not physically implemented; on reading them a ²0² is
returned whereas writing then results in a no-operation.
Pull-high resistors of each port are decided by a option
bit.
The PB0 is pin-shared with PFD signal, respectively. If
the PFD option is selected, the output signal in output
mode of PB0 will be the PFD signal. The input mode al-
ways remain its original functions. The PF0 and PC0 are
pin-shared with INT and TMR0. The INT signal is di-
rectly connected to PF0. The PFD output signal (in out-
put mode) are controlled by the PB0 data register only.
The truth table of PB0/PFD is listed below.
PBC (15H) Bit0
I
O
O
O
PB0/PFD option
x
PB0 PFD PFD
PB0 (14H) Bit0
x
D
0
1
PB0 pad status
I
D
0
PFD
Note:
²I² Input
²O² Output
²D² Data
Low Voltage Reset - LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
· The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V DD
5 .5 V
V LV R
1 .8 V
0 .9 V
V DD
5 .5 V
V LV R
0 .9 V
0V
R e s e t S ig n a l
L V R D e te c t V o lta g e
R eset
N o r m a l O p e r a tio n
R eset
*1
*2
Low Voltage Reset
Note:
²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
²*2² Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters
the reset mode.
Rev. 1.40
17
May 22, 2009
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