HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Two-Stage Inverting Amplifier
· Example
V IN
R3
R4
A0
R1
R2
A0
VO UT
· Implementation connection
VIN
R3
A0N
S11 ON
A0P
0.7VDD
0.5VDD
0.1VDD
MUX MA0P
S12 OFF
A0
EA0I
A0X
To OPA0 Interrupt
or Comparator input
R4 A0X
S13 ON
A0PS[2:0]
A1N
A1P
0.7VDD
0.5VDD
0.1VDD
A1NS[1:0]
S21 OFF
MA1N
MUX
R1
10K
MUX
MA1P
S22 OFF
R2 S23
500K ON
A1
EA1I
A1X
To OPA1 Interrupt
or Comparator input
A1PS[2:0]
A1X
S24 ON
· Two-Stage Inverting Amplifier Switch Setup
Bit
7
6
5
4
OPA2C
S24
S23
S22
S21
Setup value
1
1
0
0
Bit
OPA0C
Setup value
7
A0PS2
1
6
A0PS1
0
5
A0PS0
0
Bit
OPA1C
Setup value
7
A1G2
0
6
A1G1
0
5
A1G0
0
Switch control bits options:
S11: ON
S12: OFF
S13: ON
S21: OFF
S22: OFF
S23: ON
S24: ON
A0PS[2:0]: 100
A1PS[2:0]: 100
A1NS[1:0]: 01
A1G[2:0]: User define OPA1 Gain control
4
CPS2
0
4
A1PS2
1
3
S13
1
3
CPS1
0
3
A1PS1
0
2
S12
0
2
CPS0
0
2
A1PS0
0
1
0
S11
CXC
1
x
²x² don¢t care
1
CNS1
0
0
CNS0
0
1
A1NS1
0
0
A1NS0
1
Rev. 1.10
77
October 23, 2012