HT48R0662G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R0662G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
PAWK, PCWK, PAC~PFC, PAPU~PFPU Registers - HT48R0662G
Register
Name
PAWK
PAC
PAPU
PBC
PBPU
PCWK
PCC
PCPU
PDC
PDPU
PEC
PEPU
PFC
PFPU
POR
00H
FFH
00H
FFH
00H
00H
FFH
00H
FFH
00H
FFH
00H
03H
00H
7
PAWK7
PAC7
¾
PBC7
PBPU7
PCWK7
PCC7
PCPU7
PDC7
PDPU7
PEC7
PEPU7
¾
¾
6
PAWK6
PAC6
PAPU6
PBC6
PBPU6
PCWK6
PCC6
PCPU6
PDC6
PDPU6
PEC6
PEPU6
¾
¾
5
PAWK5
PAC5
PAPU5
PBC5
PBPU5
PCWK5
PCC5
PCPU5
PDC5
PDPU5
PEC5
PEPU5
¾
¾
Bit
4
3
PAWK4 PAWK3
PAC4 PAC3
PAPU4 PAPU3
PBC4 PBC3
PBPU4 PBPU3
PCWK4 PCWK3
PCC4 PCC3
PCPU4 PCPU3
PDC4 PDC3
PDPU4 PDPU3
PEC4 PEC3
PEPU4 PEPU3
¾
¾
¾
¾
2
PAWK2
PAC2
PAPU2
PBC2
PBPU2
PCWK2
PCC2
PCPU2
PDC2
PDPU2
PEC2
PEPU2
¾
¾
1
PAWK1
PAC1
PAPU1
PBC1
PBPU1
PCWK1
PCC1
PCPU1
PDC1
PDPU1
PEC1
PEPU1
PFC1
PFPU1
0
PAWK0
PAC0
PAPU0
PBC0
PBPU0
PCWK0
PCC0
PCPU0
PDC0
PDPU0
PEC0
PEPU0
PFC0
PFPU0
²¾² Unimplemented, read as ²0²
PAWKn/PCWKn: PA/PC wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: Pull-high function enable
0: disable
1: enable
I/O Port Control Registers
Each Port has its own control register, known as PAC, PBC, PCC, PDC, PEC, PFC which controls the
input/output configuration. With this control register, each I/O pin with or without pull-high resistors
can be reconfigured dynamically under software control. For the I/O pin to function as an input, the
corresponding bit of the control register must be written as a ²1². This will then allow the logic state of
the input pin to be directly read by instructions. When the corresponding bit of the control register is
written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output,
instructions can still be used to read the output register. However, it should be noted that the program
will in fact only read the status of the output data latch and not the actual logic status of the output pin.
Rev. 1.10
53
October 23, 2012
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