HT48R0662G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R0662G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Comparator
These devices contain a fully integrated Comparator whose operation is controlled by the Comparator
control registers, known as the CMP0C, CMP1C, COPA0C, COPA2C and COPA3C registers. The
CEN bit within CMP0C register is used as the enable or disable bit for the comparator function. The
advantages of multiple input resources, multiple reference voltage options, output polarity control,
output to Timer counter, multiple output interrupt triggers, comparator output wakeup MCU function,
comparator output with de-bounce options, comparator operating current selection and power down
control for low power consumption enhance the flexibility of this comparator to suit a wide range of
application possibilities.
Comparator Functions
The Comparator can work with OPAs or standalone as shown in the main functional blocks of the OPAs
and Comparator in this device. This comparator provides three operating current options, which are
200mA, 5mA and 1mA. The purpose of this design is to provide the suitable comparator power
consumption for different operating modes of the device. The higher the operating current, the shorter the
comparator response time, therefore, the designer can select the higher operating current for the device
working at normal mode and a lower one for the device entering power down mode. By this way, this
comparator can operate under very low power consumption and perform as a wakeup resource when the
device enters power down mode. In addition, this device provides different comparator output de-bounce
time options for different input signal. If the input signal is noise sensitive, then the better choice will be
the longer de-bounce time. The designer could select the suitable de-bounce time according to the input
signal.
CMP0C Register
Bit
7
Name
¾
R/W
¾
POR
0
6
CEN
R/W
0
5
CPOL
R/W
0
4
COUT
R
0
3
DBC1
R/W
0
2
DBC0
R/W
0
1
CPCS1
R/W
0
0
CPCS0
R/W
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3~2
Bit 1~0
unimplemented, read as ²0²
CEN: comparator on/off bit
0: off
1: on
Note that the designer should enable the comparator first before enabling the comparator
interrupt, in order to prevent an unexpected interrupt.
CPOL: comparator output polarity control bit
0: not inverted
1: inverted
COUT: comparator output bit.
CPOL=0: If the CP pin input voltage is less than CN pin, then the COUT is ²0².
If the CP pin input voltage is greater than CN pin, then the COUT is ²1².
CPOL=1: If the CP pin input voltage is less than CN pin, then the COUT is ²1².
If the CP pin input voltage is greater than CN pin, then the COUT is ²0².
DBC1, DBC0: De-bounce time selection, up to application signal
00: no de-bounce
01: de-bounce time= 1 system clock
10: de-bounce time= 4 system clock
11: de-bounce time= 16 system clock
CPCS1, CPCS0]: Comparator operating current selection for low power consumption
00: 200mA
01: 5mA
10: 1mA
11: not implemented
Rev. 1.10
81
October 23, 2012
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