HT49CA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49CA1' PDF : 58 Pages View PDF
HT49RA1/HT49CA1
Each pin on Port B can be setup via an individual config-
uration option to permit a negative transition on the pin
to wake-up the system. When a Port B pin wake-up oc-
curs, the program will resume execution at the instruc-
tion following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² be-
fore entering the Power Down Mode, the wake-up func-
tion of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Watchdog Timer
The Watchdog Timer is provided to prevent program mal-
functions or sequences from jumping to unknown loca-
tions, due to certain uncontrollable external events such
as electrical noise. It operates by providing a device reset
when the WDT counter overflows. The WDT clock is sup-
plied by one of three sources selected by configuration
option: its own self contained dedicated internal RTC os-
cillator, WDT oscillator or fSYS/4. Note that if the WDT
configuration option has been disabled, then any instruc-
tion relating to its operation will result in no operation.
In the Remote Type with LCD series of microcontrollers,
all Watchdog Timer options, such as enable/disable,
WDT clock source and clear instruction type all selected
through configuration options. There are no internal reg-
isters associated with the WDT in the Remote Type
MCU with LCD series. One of the WDT clock sources is
an internal oscillator which has an approximate period of
90ms at a supply voltage of 3V. However, it should be
noted that this specified internal clock period can vary
with VDD, temperature and process variations. The
other WDT clock source option is the fSYS/4 clock.
Whether the WDT clock source is its own internal WDT
oscillator, or from fSYS/4, it is further divided by 16 via an
internal 15-bit counter and a clearable single bit counter
to give longer Watchdog time-outs. As this ratio is fixed it
gives an overall Watchdog Timer time-out value of 215/fS
to 216/fS. As the clear instruction only resets the last
stage of the divider chain, for this reason the actual divi-
sion ratio and corresponding Watchdog Timer time-out
can vary by a factor of two. The exact division ratio de-
pends upon the residual value in the Watchdog Timer
counter before the clear instruction is executed. It is im-
portant to realise that as there are no independent inter-
nal registers or configuration options associated with
the length of the Watchdog Timer time-out, it is com-
pletely dependent upon the frequency of fSYS/4, the in-
ternal WDT oscillator or RTC oscillator.
If the fSYS/4 clock is used as the WDT clock source, it
should be noted that when the system enters the Power
Down Mode, then the instruction clock is stopped and
the WDT will lose its protecting purposes. For systems
that operate in noisy environments, using the internal
WDT oscillator is strongly recommended.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a ²HALT² instruction.
C L R W D T 1 F la g
C L R W D T 2 F la g
1 o r 2 In s tr u c tio n s
fS Y S /4
W D T O s c illa to r
R T C O s c illa to r
W D T C lo c k S o u r c e
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
W D T C lo c k S o u r c e
C o n fig u r a tio n
O p tio n
fS 1 5 - b it C o u n te r
Watchdog Timer
C LR
¸2
W D T T im e - o u t
2 15/fS ~ 2 16/fS
Rev. 1.10
39
March 30, 2014
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