HT49R10A-1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49R10A-1' PDF : 38 Pages View PDF
HT49R10A-1/HT49C10-1
time-out periods. If an RTC time-out occurs, the related
interrupt request flag (RTF; bit 4 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a
subroutine call to location 10H occurs. The real time
clock time-out signal also can be applied to be a clock
source for the timer/event counter to obtain longer
time-out periods.
RT2
0
0
0
0
1
1
1
1
RT1
0
0
1
1
0
0
1
1
RT0
0
1
0
1
0
1
0
1
RTC Clock Divided Factor
28*
29*
210*
211*
212
213
214
215
Note: ²*² not recommended for use.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
· The system oscillator turns off but the WDT or RTC
oscillator keeps running (if the WDT oscillator or the
real time clock is selected).
· The contents of the on-chip RAM and of the registers
remain unchanged.
· The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set but the TO flag is cleared.
· LCD driver is still running (if the WDT OSC or RTC
OSC is selected).
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port A, or
a WDT overflow. An external reset causes device initial-
ization, and the WDT overflow performs a ²warm reset².
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared
by system power-up or by executing the ²CLR WDT²
instruction, and is set by executing the ²HALT²
instruction. On the other hand, the TO flag is set if WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP, and leaves the others at
their original state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each pin
in port A can be independently selected to wake up the
device by configuration options. Awakening from an I/O
port stimulus, the program resumes execution of the
next instruction. On awakening from an interrupt, two
sequences may occur. If the related interrupt is disabled
or the interrupt is enabled but the stack is full, the pro-
gram resumes execution at the next instruction. But if
the interrupt is enabled, and the stack is not full, the reg-
ular interrupt response takes place.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awaken using that
interrupt.
If a wake-up event occurs, it takes 1024 tSYS (system
clock periods) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the Wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which reset may occur.
· RES is reset during normal operation
· RES is reset during HALT
· WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the ²initial condition² once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
Note:
²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES Wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT Wake-up HALT
Note: ²u² stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state. Awaking from the
HALT state, the SST delay is added.
An extra option load time delay is added during reset
and power on.
Rev. 1.50
14
July 30, 2012
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