HT49RA1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT49RA1' PDF : 58 Pages View PDF
HT49RA1/HT49CA1
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter, Time Base or RTC Inter-
rupt requires microcontroller attention, their correspond-
ing interrupt will enforce a temporary suspension of the
main program allowing the microcontroller to direct atten-
tion to their respective needs. The device contains two
external interrupts and four internal interrupt functions.
The external interrupt is controlled by the action of the ex-
ternal INT0, INT1 pin, while the internal interrupts are
controlled by the two Timer/Event Counter overflows, the
Time Base interrupt and the RTC interrupt.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the INTC0 and
INTC1 registers, which are located in the Data Memory.
By controlling the appropriate enable bits in these regis-
ter each individual interrupt can be enabled or disabled.
Also when an interrupt occurs, the corresponding re-
quest flag will be set by the microcontroller. The global
enable flag if cleared to zero will disable all interrupts.
Interrupt Operation
A Timer/Event Counter overflow, Time Base or RTC
overflow or the external interrupt line being triggered will
all generate an interrupt request by setting their corre-
sponding request flag, if their appropriate interrupt en-
able bit is set. When this happens, the Program
Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The
Program Counter will then be loaded with a new ad-
dress which will be the value of the corresponding inter-
rupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
External Interrupt 0/1
Timer/Event Counter 0/1 Overflow
Time Base Interrupt
Real Time Clock Interrupt
Priority
1/2
3/4
5
6
External Interrupt
For an external interrupt to occur, the global interrupt
enable bit, EMI, and external interrupt enable bit, EEI0,
EEI1, must first be set. Additionally the correct interrupt
edge bit must be selected to enable the external interrupt
function and to choose the trigger edge type. An actual
external interrupt will take place when the external
interrupt request flag, EIF0 or EIF1, is set, a situation that
will occur when a transition, whose type is chosen by
configuration option appears on the INT0 and, INT1 pins.
The external interrupt pins are pin-shared with the I/O
pins PB0 and PB1 and can only be configured as an
external interrupt pin if the corresponding external
interrupt enable bit in the INTC0 register have been set.
The pins must also be setup as inputs. When the interrupt
is enabled, the stack is not full and the correct transition
type appears on the external interrupt pin, a subroutine
call to the relevant external interrupt vectors at locations
04H and 08H, will take place. When the interrupt is
serviced, the external interrupt request flag, EIF0, EIF1,
will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts.
Rev. 1.10
30
March 30, 2014
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