HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
· Sleep Mode
fM, fSLOW, fSYS, fS, CPU off; fSUB, fWDT on/off depending
upon the WDT configuration option and WDT control
register.
For all devices, when the system enters the Sleep or Idle
Mode, the high frequency system clock will always stop
running. The accompanying tables shows the relation-
ship between the CLKMOD bit, the HALT instruction
and the high/low frequency oscillators. The CLMOD bit
can change normal or Slow Mode.
b7
b0
S L O W C 2 S L O W C 1 S L O W C 0 S IM ID L E L T O H T O ID L E N H L C L K C L K M O D R e g is te r
fS Y S s e le c t
1 : fM
0 : fS L O W
Id le m o d e
1 : e n a b le
0 : d is a b le
H ig h o s c illa to r r e a d y fla g
1 : tim e - o u t
0 : n o n - tim e - o u t
L o w o s c illa to r r e a d y fla g
1 : tim e - o u t
0 : n o n - tim e - o u t
S P I/I2 C c o n tin u e s r u n n in g in Id le m o d e
1 :e n a b le
0 :d is a b le
fS L O W s e le c tio n
S L O W W C 2 S L O W W C 1 S L O W W C 0 fS L O W
0
0
0
fS L
0
0
1
fS L
0
1
0
fM /6 4
0
1
1
fM /3 2
1
0
0
fM /1 6
1
0
1
fM /8
1
1
0
fM /4
1
1
1
fM /2
Clock Control Register - CLKMOD
· Operating Mode Control
Operation Mode
NORMAL Mode
SLOW0 Mode
SLOW1 Mode
IDLE Mode
SLEEP Mode
CPU
On
On
On
Off
Off
Description
fSYS
fM
fSL
fM/2 ~ fM/64
Off
Off
fSUB
On
On
On
On
On/Off
Rev. 1.30
31
December 26, 2014