HT56R24 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R24' PDF : 134 Pages View PDF
HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user
code or program is stored. The device is supplied with
One-Time Programmable, OTP, memory where users
can program their application code into the device. By
using the appropriate programming tools, OTP devices
offer users the flexibility to freely develop their applica-
tions which may be useful during debug or for products
requiring frequent upgrades or program changes.
Structure
The Program Memory has a capacity of 2K´14 to
32K´16. The Program Memory is addressed by the Pro-
gram Counter and also contains data, table information
and interrupt entries. Table data, which can be setup in
any location within the Program Memory, is addressed
by separate table pointer registers.
Device
HT56R22
HT56R23
HT56R24
HT56R25
HT56R26
Capacity
2K´14
4K´15
8K´16
16K´16
32K´16
Special Vectors
Within the Program Memory, certain locations are re-
served for special usage such as reset and interrupts.
· Reset Vector
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
· External interrupt 0/1 vector
This vector is used by the external interrupt. If the ex-
ternal interrupt pin on the device receives an edge
transition, the program will jump to this location and
begin execution if the external interrupt is enabled and
the stack is not full. The external interrupt active edge
transition type, whether high to low, low to high or both
is specified in the INTEDGE register.
· Timer/Event 0/1 counter interrupt vector
This internal vector is used by the Timer/Event Coun-
ters. If a Timer/Event Counter overflow occurs, the
program will jump to its respective location and begin
execution if the associated Timer/Event Counter inter-
rupt is enabled and the stack is not full.
· SPI/I2C interrupt vector
This internal vector is used by the SPI/I2C interrupt.
When either an SPI or I2C bus, dependent upon which
one is selected, requires data transfer, the program
will jump to this location and begin execution if the
SPI/I2C interrupt is enabled and the stack is not full.
0000H
H T56R 22
R eset
0 0 0 4 H E x te rn a l 0 In te rru p t
0 0 0 8 H E x te rn a l 1 In te rru p t
0 0 0 C H T im e r 0 In te r r u p t
0 0 1 0 H T im e r 1 In te r r u p t
0014H
0018H
S P I/I2 C In te rru p t
T im e B a s e In te r r u p t,
R T C In te rru p t,
A /D In te rru p t,
E x te r n a l P e r ip h e r a l
In te rru p t,
S P I1 In te rru p t
H T56R 23
R eset
E x te rn a l 0 In te rru p t
E x te rn a l 1 In te rru p t
T im e r 0 In te r r u p t
T im e r 1 In te r r u p t
S P I/I2 C In te rru p t
T im e B a s e In te r r u p t,
R T C In te rru p t,
A /D In te rru p t,
E x te r n a l P e r ip h e r a l
In te rru p t,
T im e r 2 In te r r u p t,
S P I1 In te rru p t
H T56R 24
R eset
E x te rn a l 0 In te rru p t
E x te rn a l 1 In te rru p t
T im e r 0 In te r r u p t
T im e r 1 In te r r u p t
S P I/I2 C In te rru p t
T im e B a s e In te r r u p t,
R T C In te rru p t,
A /D In te rru p t,
E x te r n a l P e r ip h e r a l
In te rru p t,
T im e r 2 In te r r u p t,
S P I1 In te rru p t
H T56R 25
R eset
E x te rn a l 0 In te rru p t
E x te rn a l 1 In te rru p t
T im e r 0 In te r r u p t
T im e r 1 In te r r u p t
S P I/I2 C In te rru p t
T im e B a s e In te r r u p t,
R T C In te rru p t,
A /D In te rru p t,
E x te r n a l P e r ip h e r a l
In te rru p t,
T im e r 2 In te r r u p t,
T im e r 3 In te r r u p t,
S P I1 In te rru p t
H T56R 26
R eset
E x te rn a l 0 In te rru p t
E x te rn a l 1 In te rru p t
T im e r 0 In te r r u p t
T im e r 1 In te r r u p t
S P I/I2 C In te rru p t
T im e B a s e In te r r u p t,
R T C In te rru p t,
A /D In te rru p t,
E x te r n a l P e r ip h e r a l
In te rru p t,
T im e r 2 In te r r u p t,
T im e r 3 In te r r u p t,
S P I1 In te rru p t
7FFH
Rev. 1.30
1 4 b its
FFFH
1 5 b its
1FFFH
1 6 b its
3FFFH
Program Memory Structure
1 6 b its
7FFFH
1 6 b its
19
December 26, 2014
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