HT56R25 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R25' PDF : 134 Pages View PDF
HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
Each pin on Port A can be setup via an individual config-
uration option to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up oc-
curs, the program will resume execution at the instruc-
tion following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² be-
fore entering the Power Down Mode, the wake-up func-
tion of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the Watchdog Timer counter overflows.
Watchdog Timer Operation
The Watchdog Timer clock source is provided by the in-
ternal clock, fS, which is in turn supplied by one of two
sources selected by configuration option: fSUB or fSYS/4.
Note that if the Watchdog Timer configuration option
has been disabled, then any instruction relating to its op-
eration will result in no operation.
Most of the Watchdog Timer options, such as en-
able/disable, Watchdog Timer clock source and clear in-
struction type are selected using configuration options.
In addition to a configuration option to enable the Watch-
dog Timer, there are four bits, WDTEN3~ WDTEN0, in
the MISC register to offer an additional enable control of
the Watchdog Timer. These bits must be set to a specific
value of 1010 to disable the Watchdog Timer. Any other
values for these bits will keep the Watchdog Timer en-
abled. After power on these bits will have the disabled
value of 1010.
One of the WDT clock sources is the internal fSUB, which
can be sourced from either the LXT or LIRC. The LIRC
has an approximate period of 31.2ms at a supply voltage
of 5V. However, it should be noted that this specified in-
ternal clock period can vary with VDD, temperature and
process variations. The LXT is supplied by an external
32768Hz crystal. The other Watchdog Timer clock
source option is the fSYS/4 clock. Whether the Watchdog
Timer clock source is LIRC, LXT or fSYS/4, it is divided by
213~216, using configuration option to obtain the required
Watchdog Timer time-out period. The max time out pe-
riod is when the 216 option is selected. This time-out pe-
riod may vary with temperature, VDD and process
variations. As the clear instruction only resets the last
stage of the divider chain, for this reason the actual divi-
sion ratio and corresponding Watchdog Timer time-out
can vary by a factor of two. The exact division ratio de-
pends upon the residual value in the Watchdog Timer
counter before the clear instruction is executed.
C L R W D T 1 F la g
C L R W D T 2 F la g
1 o r 2 In s tr u c tio n s
fS Y S /4
L IR C
LX T
C o n tro l
L o g ic
W D T S o u rc e
C o n fig u r a tio n
fS
O p tio n
8 - b it D iv id e r fS /2 8 7 - b it P r e s c a le r
C LR
¸2
W D T T im e - o u t
(2 13/fS , 2 14/fS , 2 15/fS o r 2 16/fS )
C o n fig O p tio n
fS /2 12, fS /2 13, fS /2 14 o r fS /2 15
Watchdog Timer
Rev. 1.30
34
December 26, 2014
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