HT56R26 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R26' PDF : 134 Pages View PDF
HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
b7
TnM 1 TnM 0 TnS TnO N TnE
b0
T M R n C R e g is te r (n = 1 )
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C o u n te r a c tiv e e d g e s e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
P u ls e W id th M e a s u r e m e n t a c tiv e e d g e s e le c t
1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e
0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1 : fS U B (3 2 7 6 8 H z o r 3 2 K R C )
0 : fS Y S /4
O p e r a tin g m o d e s e le c t
TnM 1 TnM 0
0
0 n o m o d e a v a ila b le
0
1 e v e n t c o u n te r m o d e
1
0 tim e r m o d e
1
1 p u ls e w id th m e a s u r e m e n t m o d e
Timer/Event Counter Control Register - TMRnC
Timer Control Registers -
TMR0C, TMR1C, TMR2C, TMR3C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register.
It is the Timer Control Register together with its corre-
sponding timer registers that control the full operation of
the Timer/Event Counters. Before the timers can be
used, it is essential that the appropriate Timer Control
Register is fully programmed with the right data to en-
sure its correct operation, a process that is normally car-
ried out during program initialisation.
To choose which of the three modes the timer is to oper-
ate in, either in the timer mode, the event counting mode
or the pulse width measurement mode, bits 7 and 6 of
the corresponding Timer Control Register, which are
known as the bit pair TnM1/TnM0, must be set to the re-
quired logic levels. The timer-on bit, which is bit 4 of the
Timer Control Register and known as TnON, depending
upon which timer is used, provides the basic on/off con-
trol of the respective timer. Setting the bit high allows the
counter to run, clearing the bit stops the counter. For
timers that have prescalers, bits 0~2 of the Timer Con-
trol Register determine the division ratio of the input
clock prescaler. The prescaler bit settings have no effect
if an external clock source is used. If the timer is in the
event count or pulse width measurement mode, the ac-
tive transition edge level type is selected by the logic
level of bit 3 of the Timer Control Register which is
known as TnE. An additional T1S bit in the 16-bit
Timer/Event Counter control register is used to deter-
mine the clock source for the Timer/Event Counter.
Rev. 1.30
49
December 26, 2014
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