HT56R26 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R26' PDF : 134 Pages View PDF
HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
E x te rn a l T C n
P in In p u t
T n O N - w ith T n E = 0
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r
+1
+2
+3
+4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Capture Mode Timing Chart (TnE=0)
TnPSC2~TnPSC0, which are bits 2~0 in the Timer Con-
trol Register. After the other bits in the Timer Control
Register have been setup, the enable bit TnON, which is
bit 4 of the Timer Control Register, can be set high to en-
able the Timer/Event Counter, however it will not actu-
ally start counting until an active edge is received on the
external timer pin.
If the Active Edge Select bit TnEG, which is bit 3 of the
Timer Control Register, is low, once a high to low transi-
tion has been received on the external timer pin, the
Timer/Event Counter will start counting until the external
timer pin returns to its original high level. At this point the
enable bit will be automatically reset to zero and the
Timer/Event Counter will stop counting. If the Active
Edge Select bit is high, the Timer/Event Counter will be-
gin counting once a low to high transition has been re-
ceived on the external timer pin and stop counting when
the external timer pin returns to its original low level. As
before, the enable bit will be automatically reset to zero
and the Timer/Event Counter will stop counting. It is im-
portant to note that in the pulse width capture Mode, the
enable bit is automatically reset to zero when the exter-
nal control signal on the external timer pin returns to its
original level, whereas in the other two modes the en-
able bit can only be reset to zero under program control.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the TCn pin. As the
enable bit has now been reset, any further transitions on
the external timer pin will be ignored. The timer cannot
begin further pulse width capture until the enable bit is
set high again by the program. In this way, single shot
pulse measurements can be easily made.
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external
timer pin and not by the logic level. When the Timer/Event
Counter is full and overflows, an interrupt signal is gener-
ated and the Timer/Event Counter will reload the value al-
ready loaded into the preload register and continue
counting. The interrupt can be disabled by ensuring that
the Timer/Event Counter Interrupt Enable bit in the corre-
sponding Interrupt Control Register, is reset to zero.
As the TCn pin is shared with an I/O pin, to ensure that
the pin is configured to operate as a pulse width capture
pin, two things have to happen. The first is to ensure that
the Operating Mode Select bits in the Timer Control
Register place the Timer/Event Counter in the pulse
width capture Mode, the second is to ensure that the
port control register configures the pin as an input.
Prescaler
Bits TnPSC0~TnPSC2 of the TMRnC register can be
used to define a division ratio for the internal clock
source of the Timer/Event Counter enabling longer time
out periods to be setup.
Programmable Frequency Divider - PFD
The Programmable Frequency Divider provides a
means of producing a variable frequency output suitable
for applications requiring a precise frequency generator.
The PFD output is pin-shared with the I/O pin PA3. The
PFD function is selected via configuration option, how-
ever, if not selected, the pin can operate as a normal I/O
pin.
The clock source for the PFD circuit can originate from
either Timer/Event Counter 0 or Timer/Event Counter 1
overflow signal selected via configuration option. The
output frequency is controlled by loading the required
values into the timer registers and prescaler registers to
give the required division ratio. The timer will begin to
count-up from this preload register value until full, at
which point an overflow signal is generated, causing the
PFD output to change state. The timer will then be auto-
matically reloaded with the preload register value and
continue counting-up.
For the PFD output to function, it is essential that the corre-
sponding bit of the Port A control register PAC bit 3 is setup
as an output. If setup as an input the PFD output will not
function, however, the pin can still be used as a normal in-
put pin. The PFD output will only be activated if bit PA3 is
set to ²1². This output data bit is used as the on/off control
bit for the PFD output. Note that the PFD output will be low
if the PA3 output data bit is cleared to ²0².
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very pre-
cise values of frequency can be generated.
Bits TnPSC0~TnPSC2 of the control register can be
used to define the pre-scaling stages of the internal
clock source of the Timer/Event Counter. The
Rev. 1.30
55
December 26, 2014
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